HARDWARE ARCHITECTURE FOR OBJECT DETECTION BASED ON ADABOOST ALGORITHM

Hui Xu, Feng Zhao, Ran Ju

2010

Abstract

This paper implements a hardware architecture for object detection based on AdaBoost learning algorithm and Haar-like features. To increase detection speed and reduce hardware consumption, an integral image calculation array with pipelined feature data flow are introduced. Input images are scanned by sub-windows and detected by cascade classifiers. Moreover, special design is made to enhance the parallelism of the architecture. In comparison with the original design, detection speed is improved by three, with only 5% increase in hardware consumption. The final hardware detection system, implemented on Xilinx V2pro FPGA platform, reaches the detection speed of 80 f ps and consumes 91% resources of the platform.

Paper Citation

in Harvard Style

Xu H., Zhao F. and Ju R. (2010). HARDWARE ARCHITECTURE FOR OBJECT DETECTION BASED ON ADABOOST ALGORITHM . In Proceedings of the International Conference on Computer Vision Theory and Applications - Volume 2: VISAPP, (VISIGRAPP 2010) ISBN 978-989-674-029-0, pages 420-424. DOI: 10.5220/0002841204200424

in Bibtex Style

@conference{visapp10,
author={Hui Xu and Feng Zhao and Ran Ju},
title={HARDWARE ARCHITECTURE FOR OBJECT DETECTION BASED ON ADABOOST ALGORITHM},
booktitle={Proceedings of the International Conference on Computer Vision Theory and Applications - Volume 2: VISAPP, (VISIGRAPP 2010)},
year={2010},
pages={420-424},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0002841204200424},
isbn={978-989-674-029-0},
}

in EndNote Style

TY - CONF
JO - Proceedings of the International Conference on Computer Vision Theory and Applications - Volume 2: VISAPP, (VISIGRAPP 2010)
TI - HARDWARE ARCHITECTURE FOR OBJECT DETECTION BASED ON ADABOOST ALGORITHM
SN - 978-989-674-029-0
AU - Xu H.
AU - Zhao F.
AU - Ju R.
PY - 2010
SP - 420
EP - 424
DO - 10.5220/0002841204200424