ADDRESSING THE HARDWARE RESOURCE REQUIREMENTS OF NETWORK-ON-CHIP BASED NEURAL ARCHITECTURES

Sandeep Pande, Fearghal Morgan, Seamus Cowley, Brian Mc Ginley, Jim Harkin, Snaider Carrillo, Liam Mc Daid

2011

Abstract

Network on Chip (NoC) based Spiking Neural Network (SNN) hardware architectures have been proposed as embedded computing systems for data/pattern classification and control applications. As the NoC communication infrastructure is fully reconfigurable, scaling of these systems requires large amounts of distributed on-chip memory for storage of the SNN synaptic connectivity (topology) information. This large memory requirement poses a serious bottleneck for compact embedded hardware SNN implementations. The goal of this work is to reduce the topology memory requirement of embedded hardware SNNs by exploring the combination of fixed and configurable interconnect through the use of fixed sized clusters of neurons and NoC communication infrastructure. This paper proposes a novel two-layered SNN structure as a neural computing element within each neural tile. This architectural arrangement reduces the SNN topology memory requirement by 50%, compared to a non-clustered (single neuron per neural tile) SNN implementation. The paper also proposes sharing of the SNN topology memory between neural cluster outputs within each neural tile, for utilising the on-chip memory efficiently. The paper presents hardware resource requirements of the proposed architecture by mapping SNN topologies with random and irregular connectivity patterns (typical of practical SNNs). The architectural scheme of sharing the SNN topology memory between neural cluster outputs, results in efficient utilisation of the SNN topology memory and helps accommodate larger SNN applications on the proposed architecture. Results illustrate up to a 66% reduction in the required silicon area of the proposed clustered neural tile SNN architecture using shared topology memory compared to the non-clustered, non-shared memory architecture.

Paper Citation

in Harvard Style

Pande S., Morgan F., Cowley S., Mc Ginley B., Harkin J., Carrillo S. and Mc Daid L. (2011). ADDRESSING THE HARDWARE RESOURCE REQUIREMENTS OF NETWORK-ON-CHIP BASED NEURAL ARCHITECTURES . In Proceedings of the International Conference on Neural Computation Theory and Applications - Volume 1: NCTA, (IJCCI 2011) ISBN 978-989-8425-84-3, pages 128-137. DOI: 10.5220/0003676601280137

in Bibtex Style

@conference{ncta11,
author={Sandeep Pande and Fearghal Morgan and Seamus Cowley and Brian Mc Ginley and Jim Harkin and Snaider Carrillo and Liam Mc Daid},
title={ADDRESSING THE HARDWARE RESOURCE REQUIREMENTS OF NETWORK-ON-CHIP BASED NEURAL ARCHITECTURES},
booktitle={Proceedings of the International Conference on Neural Computation Theory and Applications - Volume 1: NCTA, (IJCCI 2011)},
year={2011},
pages={128-137},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0003676601280137},
isbn={978-989-8425-84-3},
}

in EndNote Style

TY - CONF
JO - Proceedings of the International Conference on Neural Computation Theory and Applications - Volume 1: NCTA, (IJCCI 2011)
TI - ADDRESSING THE HARDWARE RESOURCE REQUIREMENTS OF NETWORK-ON-CHIP BASED NEURAL ARCHITECTURES
SN - 978-989-8425-84-3
AU - Pande S.
AU - Morgan F.
AU - Cowley S.
AU - Mc Ginley B.
AU - Harkin J.
AU - Carrillo S.
AU - Mc Daid L.
PY - 2011
SP - 128
EP - 137
DO - 10.5220/0003676601280137