PHASE LOCKED LOOPS DESIGN AND ANALYSIS

Nikolay V. Kuznetsov, Gennady A. Leonov, Svetlana S. Seledzhi

2008

Abstract

New methods, for the design of different block diagrams of PLL, using the asymphtotic analysis of high-frequency periodic oscillations, are suggested. The PLL description on three levels is made: 1) on the level of electronic realizations; 2) on the level of phase and frequency relations between inputs and outputs in block diagrams; 3) on the level of differential and integro-differential equations. On the base of such description, the block diagram of floating PLL for the elimination of clock skew and that of frequency synthesizer is proposed. The rigorous mathematical formulation of the Costas loop for the clock oscillators are first obtained. The theorem on a PLL global stability is proved.

Paper Citation

in Harvard Style

Kuznetsov N., Leonov G. and Seledzhi S. (2008). PHASE LOCKED LOOPS DESIGN AND ANALYSIS . In Proceedings of the Fifth International Conference on Informatics in Control, Automation and Robotics - Volume 3: ICINCO, ISBN 978-989-8111-32-6, pages 114-118. DOI: 10.5220/0001485401140118

in Bibtex Style

@conference{icinco08,
author={Nikolay V. Kuznetsov and Gennady A. Leonov and Svetlana S. Seledzhi},
title={PHASE LOCKED LOOPS DESIGN AND ANALYSIS},
booktitle={Proceedings of the Fifth International Conference on Informatics in Control, Automation and Robotics - Volume 3: ICINCO,},
year={2008},
pages={114-118},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0001485401140118},
isbn={978-989-8111-32-6},
}

in EndNote Style

TY - CONF
JO - Proceedings of the Fifth International Conference on Informatics in Control, Automation and Robotics - Volume 3: ICINCO,
TI - PHASE LOCKED LOOPS DESIGN AND ANALYSIS
SN - 978-989-8111-32-6
AU - Kuznetsov N.
AU - Leonov G.
AU - Seledzhi S.
PY - 2008
SP - 114
EP - 118
DO - 10.5220/0001485401140118