A 640 MBIT/S 32-BIT PIPELINED IMPLEMENTATION OF THE AES ALGORITHM

Guido Marco Bertoni, Luca Breveglieri, Roberto Farina, Francesco Regazzoni

2008

Abstract

Due to the diffusion of cryptography in real time applications, performances in cipher and decipher operations are nowadays more important than in the past. On the other side, while facing the problem for embedded systems, additional constraints of area and power consumption must be considered. Many optimized software implementations, instruction set extensions and co-processors, were studied in the past with the aim to either increase performances or to keep the cost low. This paper presents a co-processor that aims to be an intermediate solution, suitable for such applications that require a throughput in the Megabit range and where the die size is a bit relaxed as constraint. To achieve this goal, the core is designed to operate at 32 bits and the throughput is guaranteed by a 2 stage pipeline with data forwarding. The obtained results synthesizing our coprocessor by means of the CMOS 0.18 µm standard cell library show that the throughput reaches 640 Mbit/s while the circuit size is of only 20 K equivalent gates.

Paper Citation

in Harvard Style

Marco Bertoni G., Breveglieri L., Farina R. and Regazzoni F. (2008). A 640 MBIT/S 32-BIT PIPELINED IMPLEMENTATION OF THE AES ALGORITHM . In Proceedings of the International Conference on Security and Cryptography - Volume 1: SECRYPT, (ICETE 2008) ISBN 978-989-8111-59-3, pages 453-459. DOI: 10.5220/0001925504530459

in Bibtex Style

@conference{secrypt08,
author={Guido Marco Bertoni and Luca Breveglieri and Roberto Farina and Francesco Regazzoni},
title={A 640 MBIT/S 32-BIT PIPELINED IMPLEMENTATION OF THE AES ALGORITHM},
booktitle={Proceedings of the International Conference on Security and Cryptography - Volume 1: SECRYPT, (ICETE 2008)},
year={2008},
pages={453-459},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0001925504530459},
isbn={978-989-8111-59-3},
}

in EndNote Style

TY - CONF
JO - Proceedings of the International Conference on Security and Cryptography - Volume 1: SECRYPT, (ICETE 2008)
TI - A 640 MBIT/S 32-BIT PIPELINED IMPLEMENTATION OF THE AES ALGORITHM
SN - 978-989-8111-59-3
AU - Marco Bertoni G.
AU - Breveglieri L.
AU - Farina R.
AU - Regazzoni F.
PY - 2008
SP - 453
EP - 459
DO - 10.5220/0001925504530459