Modeling and Simulation of Logic Gates using DEVS

Maamar Hamri, Nesrine Driouche

2015

Abstract

Discrete event simulation becomes popular more and more and was applied successfully in many fields: medicine, robotics, etc. One of this field is digital circuits for which boolean logics is the basis of computation by designing logic gates. However such a paradigm does not consider the time basis. Consequently, the boolean logic paradigm can not design and simulate delays of circuits and stamped explicitly computations. In this paper, we propose to combine the boolean logic paradigm and Discrete EVent system Specification (DEVS) formalism for modeling and simulation logic gates. Using this approach, we are able to design complex network of logic gates by reusing and coupling basic ones and to analyze behavior through time.

Paper Citation

in Harvard Style

Hamri M. and Driouche N. (2015). Modeling and Simulation of Logic Gates using DEVS . In Proceedings of the 5th International Conference on Simulation and Modeling Methodologies, Technologies and Applications - Volume 1: SIMULTECH, ISBN 978-989-758-120-5, pages 212-218. DOI: 10.5220/0005567202120218

in Bibtex Style

@conference{simultech15,
author={Maamar Hamri and Nesrine Driouche},
title={Modeling and Simulation of Logic Gates using DEVS},
booktitle={Proceedings of the 5th International Conference on Simulation and Modeling Methodologies, Technologies and Applications - Volume 1: SIMULTECH,},
year={2015},
pages={212-218},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0005567202120218},
isbn={978-989-758-120-5},
}

in EndNote Style

TY - CONF
JO - Proceedings of the 5th International Conference on Simulation and Modeling Methodologies, Technologies and Applications - Volume 1: SIMULTECH,
TI - Modeling and Simulation of Logic Gates using DEVS
SN - 978-989-758-120-5
AU - Hamri M.
AU - Driouche N.
PY - 2015
SP - 212
EP - 218
DO - 10.5220/0005567202120218